The present invention relates to the design of integrated circuits (ICs) using computer-aided design and computer-aided engineering programs (CAD/CAE). In particular, the present invention relates to CAD/CAE programs that optimize the design of an IC.
The design process for an integrated circuit (IC) is a process of transforming a specification for desired logic or analog functions to a physical or geometric arrangement for an IC die that can -perform the desired functions. Modern integrated circuits, particularly VLSI circuits, are very complex and various stages in the design process are automated using CAD/CAE software tools.
Typically, a technology mapping program will be used to convert a specification into an arrangement of library elements, such as gates, and interconnections. The output of the technology mapping process is a trial netlist which lists the library elements used and their interconnections, also called nodes. The technology mapping process is iterative and several trial netlists may be tried before an accepted netlist is found that has acceptable delays for each node based on a simplified delay calculation performed as part of the technology mapping. This simplified delay calculation, however, does not take into account the physical placement of the elements or interconnections.
Next, a physical placement program is used to specify geometric locations for each library element and also a geometric path for each interconnect. After a trial physical placement is made, a more complex delay calculation is made that takes into account the physical placement of the library elements and the interconnections. As the more complex delay calculation identifies critical nodes with excessive delays, the physical placement is iteratively repeated to reduce the delay to an acceptable amount. In some cases, the delay does not converge to an acceptable delay, and development activity returns to the technology mapping program to generate another accepted netlist to be tried by the physical placement program.
At the end of the process, an accepted netlist and global placement are created that may satisfy the delay requirements, however, because of the limitations of the simple delay calculations made in the technology mapping program, the netlist and global placement may not be optimized well for implementation as an IC.
A program is needed that will optimize the netlist and the global placement without, the limitations imposed by the simple delay calculations in the technology mapping used to generate the netlist.
Disclosed is a computer program that improves a netlist of logic nodes and physical placement for an IC. The program (a) identifies critical nodes based on delay information calculated from the physical placement. Then the program (b) selects a set of critical nodes and optimally collapses their critical fan-ins and part of the non-critical fan-ins based on their Boolean relationship, which includes at least one critical node. After that, the program (c) remaps the collapsed sub-netlist by covering its subject graph with an optimal pattern graph, and by dynamically estimating and updating the fanout loads. The program returns to step (b) if the remapped sub-netlist is unacceptable, and returns to step (a) after updating the delay information and coordinates of newly mapped gates if the remapped sub-netlist is acceptable. The program exits at step (a) when no more critical nodes are identified at step (a)